1. Field of the Invention
Example embodiments relate to an overlay key used in a semiconductor manufacturing process. More particularly, example embodiments relate to an overlay key for measuring overlay accuracy between patterned layers stacked on a semiconductor substrate, method of forming the overlay key and method of measuring the overlay accuracy using the overlay key.
2. Description of the Related Art
Generally, a semiconductor device is manufactured by repeatedly forming patterned layers on a semiconductor substrate such as a silicon wafer, for example. The patterned layers may be formed by one or more layer formation processes including, but not limited to, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition, etc., and may be patterned by a photolithography process and/or an etching process, for example.
The overlay accuracy between the patterned layers may be measured using an overlay key formed in the patterned layers. In general, a conventional overlay key may include a lower overlay pattern formed in a lower layer and an upper overlay pattern formed on an upper layer. A conventional overlay key may have a box-in-box shape.
The overlay accuracy may be determined by measuring the alignment accuracy between the lower and upper overlay patterns, and an alignment correction value between a semiconductor substrate and a photo mask (or reticle) may be determined according to the overlay accuracy in a photolithography process.
As the packing density of semiconductor devices increase, the significance of measuring the overlay accuracy generally increases.